module SHL2#(parameter WIDTH = 32) (
        input wire [WIDTH-1:0] SHL2input,
        output reg [((WIDTH == 32) ? WIDTH : WIDTH+2) - 1:0] SHL2output
    );

    always @(*) begin
        if (WIDTH == 32) begin
            SHL2output = SHL2input << 2;
        end else if (WIDTH == 26) begin
            SHL2output = SHL2input << 2;
        end else begin
            // Handle other cases or provide a default behavior
            SHL2output = 0;
        end
    end

endmodule
